(apologies if these are trivial questions -- it seems like the info on
variables and scope/exports is sort of scattered across chapters in the
make manual.)
i think i finally got a grip on variables. as i see it, when i invoke
"make", i can define variables in one of three ways:
a) $ export FOO=bar
$ make ...
b) $ FOO=bar make ...
c) $ make FOO=bar ...
techniques a) and b) above are effectively identical (at least from the
point of view of the make command) since they both define a variable in
the *shell's* environment to be passed to the make command, correct? the
only difference, of course, is whether the FOO env variable still exists
after the call to make, but strictly from the perspective of the make
command, approaches a) and b) are identical, right?
next, in all three cases, as long as i don't try to mess with the value
of FOO in the makefiles, that variable will be available throughout *all*
recursive make calls, correct?
there *is*, of course, a difference between a)/b) and c) in that, in the
docs, a) and b) refer to getting a variable from the "environment", while
c) is described as getting a variable value as a "command argument", and
those situations are clearly processed differently depending on whether
you want to override that value in the makefile, etc. that is, a simple
assignment in a makefile will override a value coming in as part of the
*environment*, but not as a command argument (unless you use the
"override" directive, etc.). is this accurate so far?
if so, one more question. does all this hold when i make a recursive
make call? that is, if i define a variable within a makefile and "export"
it, does it have all the properties of a regular environment variable that
i would have received from the shell, as opposed to passing that variable
as a command argument?
more later, i'm sure, as i slowly get unconfused.
rday
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