Hi,
thank you very much for that hint, now it works!
But this changes my understanding of how "make" works,
i wrote the rules for SRC and OBJ with the normal "="
sign, explicitly NOT "=:".
Did i miss something in the documentation about variable
expansion in Makefiles? To my (previous) understanding
the order of lines with normal assignments ("=") should
never matter.
I thought make internally builds a graph of the dependencies
and also expands variables built on that.
It would be great if anybody could give me some hints
regarding this issue.
Best regards,
Torsten.
> > final.elf: $(OBJ) $(DEP)
> > $(LD) -o $@ $(OBJ)
>
> You need to move this to after where you set OBJ. At the point that you
> declare the target here, OBJ is empty.
>
> Also you don't need the dependency on $(DEP) because final.elf doesn't
> really depend on them. Make will try to create them automatically once you
> "include" them.
>
> It might be wiser to use $^ (list of all prerequisites) instead of $(OBJ)
> explicitly in the command. That way you would see when the prerequisites
> aren't set correctly.
>
> # somewhere after OBJ is defined.
> final.elf: $(OBJ)
> $(LD) -o $@ $^
>
> Best regards,
> Ian
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