This catch for me was that the rules for the generated source files were also generated! So in my system there are two Makefile fragments that get included.
tbdep.mak - Which contains rules to generate source files
vhdldep.mak - Which contains rules to compile all the source files (and should include the generated sources)
At the moment I can get this simple example working, but there is something going wrong with my full build.
tbdep.mak : Makefile echo "generated1 :" > tbdep.mak.fail echo " touch generated1" >> tbdep.mak.fail echo >> tbdep.mak.fail echo "generated2 :" >> tbdep.mak.fail echo " touch generated2" >> tbdep.mak.fail echo >> tbdep.mak.fail echo "GENERATED_VHDL := generated1 generated2" >> tbdep.mak.fail /bin/mv tbdep.mak.fail tbdep.mak
include tbdep.mak
vhdldep.mak : ${GENERATED_VHDL}
echo "compile:" > vhdldep.mak.fail
echo " @echo Compiling ${GENERATED_VHDL}" >> vhdldep.mak.fail
/bin/mv vhdldep.mak.fail vhdldep.makinclude vhdldep.mak
clobber: /bin/rm -rf vhdldep.mak tbdep.mak /bin/rm -rf generated1 generated2
When I run make compile, Make first builds its two fragment files. The first time it builds vhdldep.mak it is incomplete because the generated sources have not been created yet. But then it builds the generated sources and this does re-build vhdldep.mak correctly. I was a bit worried that it would not re-evaluate the ${GENERATED_VHDL} variable, but it does. In the end, this example works, the "compile" target runs and echos the names of the generated files.
Unfortunately in my full build vhdldep.mak is NOT being rebuilt a 2nd time. I can not figure out why at the moment, it must be something silly I am not spotting.
[/tmp]$ make compile Makefile:12: tbdep.mak: No such file or directory Makefile:20: vhdldep.mak: No such file or directory echo "compile:" > vhdldep.mak.fail echo " @echo Compiling " >> vhdldep.mak.fail /bin/mv vhdldep.mak.fail vhdldep.mak echo "generated1 :" > tbdep.mak.fail echo " touch generated1" >> tbdep.mak.fail echo >> tbdep.mak.fail echo "generated2 :" >> tbdep.mak.fail echo " touch generated2" >> tbdep.mak.fail echo >> tbdep.mak.fail echo "GENERATED_VHDL := generated1 generated2" >> tbdep.mak.fail /bin/mv tbdep.mak.fail tbdep.mak touch generated1 touch generated2 echo "compile:" > vhdldep.mak.fail echo " @echo Compiling generated1 generated2" >> vhdldep.mak.fail /bin/mv vhdldep.mak.fail vhdldep.mak Compiling generated1 generated2
Paul D. Smith wrote:
%% Jason Pearce <[EMAIL PROTECTED]> writes:
jp> VHDL_SOURCES := $(wildcard *.vhd)
jp> vhdldep.mak : ${VHDL_SOURCES} jp> perl vhdldep.pl -t mak ${VHDL_SOURCES} > vhdldep.makfail jp> # sleep 1 jp> /bin/mv vhdldep.makfail vhdldep.mak
jp> include vhdldep.mak
jp> sources:: generated1.vhd
jp> generated1.vhd : generated1.vhd.m4
jp> m4 generated1.vhd.m4 > generated1.vhd.fail
jp> /bin/mv generated1.vhd.fail generated1.vhd
jp> sources:: generated2.vhd
jp> generated2.vhd : generated1.vhd.m4 jp> m4 generated2.vhd.m4 > generated2.vhd.fail jp> /bin/mv generated2.vhd.fail generated2.vhd
Hm. If I understand what you're doing, I would avoid this two-step operation by having the .mak file depend on the actual files. Does something like this do what you want:
VHDL_SOURCES := $(wildcard *.vhd) vhdldep.mak : generated1.vhd generated2.vhd ${VHDL_SOURCES} perl vhdldep.pl -t mak *.vhd > vhdldep.makfail /bin/mv vhdldep.makfail vhdldep.mak
include vhdldep.mak
generated1.vhd : generated1.vhd.m4 m4 generated1.vhd.m4 > generated1.vhd.fail /bin/mv generated1.vhd.fail generated1.vhd
generated2.vhd : generated1.vhd.m4 m4 generated2.vhd.m4 > generated2.vhd.fail /bin/mv generated2.vhd.fail generated2.vhd
?? I think it should.
Also, I would definitely use make variables for perl, m4, and /bin/mv rather than writing them out directly... :-).
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