$(eval) can not currently be used to define new rules (and actually
makes make core-dump) and thus I need help to solve the following
problem:
I need to have a work-alike to what this Makefile intends to do (but
does not as eval does not work):
-----{Makefile}-----
#### Dependencies ####
.PHONY: %.deps
%.deps: %.mk
$(eval include $<)
#### Images ####
%.pnm: %.jpg
jpegtopnm $< > $@
%.tiff: %.pnm
pnmtotiff $< > $@
%.eps: %.tiff %.size
tiff2ps -e -3 $< > $@
#### Texts ####
%.texml: %.xml %.texml.deps
xsltproc poetry.texml.xsl $< > $@
%.texml.mk: %.xml
xsltproc --stringparam filename $* poetry.texml.deps.xsl $< > $@
%.latex: %.texml
texml $< $@
%.html: %.xml %.html.deps
xsltproc poetry.html.xsl $< > $@
%.html.mk: %.xml
xsltproc --stringparam filename $* poetry.html.deps.xsl $< > $@
# Catch-all
%.mk:
touch $@
#### Output ####
%.toc %.log %.aux: %.latex
latex $*.latex
%.dvi: %.latex %.toc
latex $*.latex
%.ps: %.dvi
dvips -o $@ $<
-----{/Makefile}-----
That is, auto-calculate dependencies for making a target when one knows
that that target may have to be made. This can not be replaced with a
static rule to calculate all automatic dependencies, as that would be
way too much in some cases (%.texml: %.xml %.texml.deps in the above
code matches _many_ files).
Is it possible to have make re-start the current run with a new make-
file, similarly to "exec" in the shell?
Regards,
Egil
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