Try factoring out the commonalities and "include" them. Ken
On Fri, Aug 12, 2005 at 05:42:10PM +0300, Angel Tsankov wrote: > I've noticed that some of my makefiles differ only in: > output file name; > extension of source files; > compiler that is to be invoked; > compiler options; > > All the rest is the same - variables, functions and targets. > Provided this, how can I reduce duplication of code in makefiles? > > Angel Tsankov > [EMAIL PROTECTED] > > > _______________________________________________ > Help-make mailing list > [email protected] > http://lists.gnu.org/mailman/listinfo/help-make _______________________________________________ Help-make mailing list [email protected] http://lists.gnu.org/mailman/listinfo/help-make
