What you can do, if it is useful to you, is to have the top level makefile
include all sub-makefiles and, as each one loads, it can append text to a
variable defined in the top level makefile. You would need to design the
makefiles so that there is no undesirable name collision since all would
have access to all variables from all makefiles.
I use a system like this, in which makefiles are clearly organized,
differentiating files which define variables from makefiles which define
rules so that the rules makefiles are loaded in the proper order. You need
to be very familiar with how make reads makefiles for this to work.
- Greg
At 08:36 PM 8/27/2005 -0400, Paul D. Smith wrote:
%% [EMAIL PROTECTED] writes:
l> Hi, im trying to write a makefile to manage a C++ object oriented
l> project. I have a top level makefile that defines and exports a
l> variable. When i call a sub-makefile this variable gets new text
l> appended to it. I need to use the new text in the top-level
l> makefile, but when make finishes the processing of the sub-makefile
l> the text that was appended dissapear. How can I use in a top-level
l> makefile the values that a sub-makefile appends to a exported
l> variable?
You can't. Every recursive invocation of make is a separate process,
every process has its own set of variables, and the variable settings in
that process cannot be passed back to the parent process. Just like
when you start a new shell and change a variable there, it cannot
propagate back up to the process that invoked the shell.
--
-------------------------------------------------------------------------------
Paul D. Smith <[EMAIL PROTECTED]> Find some GNU make tips at:
http://www.gnu.org http://make.paulandlesley.org
"Please remain calm...I may be mad, but I am a professional." --Mad
Scientist
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