Paul, That's the conclusion I came to from the manual & my experimentation: targets and prerequisite lists are expanded immediately, and commands are deferred. Then, I started wondering how pattern rules worked.
I hoped that, since section 3.9 "How make Reads a Makefile" says "During the first phase it ... internalizes all the variables and their values, implicit and explicit rules, and constructs a dependency graph of all the targets and their prerequisites", it would be able to treat the "%.lib: $(%.lib_objs)" pattern rule just like it does the "%.o: %.c" pattern rule, and translate the $(%.lib_objs) variable only when it needed to, ie: when it had the target name that matched the "%.lib" pattern. I don't see why it wouldn't be able to do that. I guess it's not that it can't, but just that it hasn't been done, and that I should look at this as an opportunity to finally be able to give back something useful to the open source community by implementing this behavior as an enhancement to Make. Do you agree with me that this would be a valuable addition to how Make handles variables? Alternatively, can you recommend any other way to derive the prerequisite list from the target that caused this rule to be hit? Isn't that what static pattern rules are for? Of course, completing such an enhancement would incur the inevitable learning curve I would require to become familiar with the Make code. Make would scan the list of the variables it had previously internalized to find the first one that matched the "%.lib: $(%.lib_objs)" pattern rule _before_ expanding that variable to form the prerequisite. Right now, I guess the % character in a variable doesn't have any special meaning, like "% = stem" - it's just another character, like 'a','b', or 'c'. In that case, I guess pattern rules are actually _filename_ pattern rules, ie: limitted to matching pattern found in filenames, not variables. Jean. -----Original Message----- From: Paul Smith Sent: Tuesday, September 06, 2005 11:01 AM To: Boucher, Jean Cc: [email protected] Subject: RE: Pattern rule prereqs are variables with % in them %% "Jean" writes: bj> %.lib: $(%.lib_objs) $(%.lib_libs) bj> @echo 'Hit .lib .lib_objs pattern rule for $@, prereqs=$^';\ You can't do this. Variable and function references in target and prerequisite lists are expanded immediately when the makefile is read in. The "%" in patterns is not filled in until later, when make is trying to find a rule to build a target. So, these references to variables '%.lib_objs' and '%.lib_libs' are expanding to the empty string. -- ------------------------------------------------------------------------ ------- Paul D. Smith <[EMAIL PROTECTED]> Find some GNU make tips at: http://www.gnu.org http://make.paulandlesley.org "Please remain calm...I may be mad, but I am a professional." --Mad Scientist ======================================================================== CONFIDENTIALITY NOTICE ---------------------- This message, together with any attachments, may be legally privileged and is confidential information intended only for the use of the individual or entity to which it is addressed. It is exempt from disclosure under applicable law including court orders. If you are not the intended recipient, you are hereby notified that any use, dissemination, distribution or copy of this message, or any attachment, is strictly prohibited. If you have received this message in error, please notify the original sender and delete this message, along with any attachments, from your computer. _______________________________________________ Help-make mailing list [email protected] http://lists.gnu.org/mailman/listinfo/help-make
