I'm trying to do
something like this:
# BEGIN
Makefile
Targets = a b
a_sources = a.cpp b.cpp
a_libs = bepa cepa
a_libs = bepa cepa
b_sources = c.cpp
b_libs = depa
b_libs = depa
libs = $([EMAIL PROTECTED])
sources = $([EMAIL PROTECTED])
sources = $([EMAIL PROTECTED])
all : $(Targets)
$(Targets): % : $(%_libs)
@echo Target $@:
@echo Target $@:
@echo libs: $(libs)
@echo sources: $(sources)
@echo
@echo sources: $(sources)
@echo
#
build a lot of stuff here based on $(libs) and $(sources)
.PHONY: all $(Targets)
# END
Makefile
Calling 'make' for
this file will result in a correct listing of the sources and libs for each
target. The problem is that the prerequisites for targets seem to be the value
of the variable '%_libs' rather than the value of 'a_libs' for target 'a'
or 'b_libs' for target 'b', which of course was intended.
Is there any way of
making the prereqs evaluate '%' and construct the variable name correctly before
evaluating the variable?
BTW,
neither
$(Targets):
$(libs)
nor
$(Targets): % :
$(libs)
does the
trick!
Hoping for
help!
/Anna
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