The code in the template is summarized as
include target_defs.mk
ifeq ("$(words ${module})", "1")
# Default, only one module to build from sources in a target directory.
${module} : platform_module
else
# Assumes each module has a corresponding <module>_source
#
$(foreach m,${module}, \
$(eval $(call make-module-tgt, ${m}, $(subst .c,.o, ${${m}_sources})) ) \
)
endif
The function/macro defined in the included file is:
# $(call make-module-tgt, target, obj_list )
define make-module-tgt
${1}: ${2}
${LD} ${LDFLAGS} -o ${1} ${2} ${LIBS}
endef
With this code, make fails with "*** missing `endif'. Stop."
If I replace the $(eval ) with $(warning ), no errors appear and the target is generated correctly.
If I comment out the code such that just the foreeach function remains, the make succeeds.
make version: 3.80, compiled on Solaris
Suggestions?
Much thanks in advance!
--Eric
--
E r i c W e s t
[EMAIL PROTECTED]
Boston, Ma USA
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