Every logical line in a command script is invoked in a separate shell.
If you have a complex command that spans multiple physical lines in a
makefile you must add backslashes to the end so they are considered one
logical line and passed to the same shell.
Using define / endef does _NOT_ absolve you of this responsibility:
every separate logical line in a defined variable is considered a
separate logical line when the variable is expanded.
So:
define copy_mi_proj
if ! test -f ${SRC_TREE}/$(1)/make.include ; then
${EXEC_LOG} $(CP) ${MAKEINC_DIR}/make.include.$(1)
${SRC_TREE}/$(1)/make.include -proj $(1) ;
fi
endef
foo:
@$(copy_mi_proj)
Is identical to writing:
foo:
if ! test -f ${SRC_TREE}/$(1)/make.include ; then
${EXEC_LOG} $(CP) ${MAKEINC_DIR}/make.include.$(1)
${SRC_TREE}/$(1)/make.include -proj $(1) ;
fi
which is obviously bogus.
PS. When debugging makefiles it's best to leave off the "@" prefix so
that you can see what make is doing. You can add them back later
once you know things work.
--
-------------------------------------------------------------------------------
Paul D. Smith <[EMAIL PROTECTED]> Find some GNU make tips at:
http://www.gnu.org http://make.paulandlesley.org
"Please remain calm...I may be mad, but I am a professional." --Mad Scientist
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