%% ody13 <[EMAIL PROTECTED]> writes: o> I got a trivial Makefile looking like this, can someone tell me why o> all the objects are rebuild everytime make is called? Any help is o> appreciated.
o> THISBINDIR = $(BRANCH)$(BINDIR) o> .cpp.o: o> $(ccc) $(INCLUDES) $(CCFLAGS) -c $< -o $(THISBINDIR)$@ o> .c.o: o> $(ccc) $(INCLUDES) $(CCFLAGS) -c $< -o $(THISBINDIR)$@ You're violating a basic principle of make: your rules say that they will build "foo.o" but they really build "$(THISBINDIR)/foo.o". Because of this, the targets make is looking for never get updated and so make will keep trying to build them. See the Rules for Makefiles and the info on VPATH on my website below for more details about this issue. -- ------------------------------------------------------------------------------- Paul D. Smith <[EMAIL PROTECTED]> Find some GNU make tips at: http://www.gnu.org http://make.paulandlesley.org "Please remain calm...I may be mad, but I am a professional." --Mad Scientist _______________________________________________ Help-make mailing list [email protected] http://lists.gnu.org/mailman/listinfo/help-make
