Makefile:46: *** commands commence before first target. Stop.
-----Original Message-----
From: Paul Smith [mailto:[EMAIL PROTECTED] On Behalf Of Paul D. Smith
Sent: Monday, March 20, 2006 9:51 AM
To: PATTON, BILLY (SBCSI)
Cc: [email protected]
Subject: Re: Must be very simple
%% "PATTON, BILLY \(SBCSI\)" <[EMAIL PROTECTED]> writes:
pb> It must be a very obvious problem that I can't see.
pb> define inc_proj
pb> if test -f $(SRC_TREE)/$(1)/make.include ; then \
pb> include $(SRC_TREE)/$(1)/make.include ; \
pb> -include $(SRC_TREE)/$(1)/make.dependencies ; \
pb> else \
pb> include $(MAKEINC_DIR)/$(1).make.include ; \
pb> -include $(MAKEINC_DIR)/$(1).make.dependencies ; \
pb> fi
pb> endef
The above is a shell script.
pb> $(foreach proj,${PROJECTS},$(eval $(call inc_proj,$(proj))))
This will generate a bunch of instances of the shell script in the
makefile and make will try to read them as make commands; they aren't
legal make commands.
You have to put the foreach into a script context (precede it with a TAB
in a rule context).
pb> If I change eval to warning I don't get the message.
Sure, because warning doesn't evaluate to anything (it just prints
things), so there's nothing for make to read in and thus no syntax
error.
--
------------------------------------------------------------------------
-------
Paul D. Smith <[EMAIL PROTECTED]> Find some GNU make tips at:
http://www.gnu.org http://make.paulandlesley.org
"Please remain calm...I may be mad, but I am a professional." --Mad
Scientist
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