On 7/17/06, ma <[EMAIL PROTECTED]> wrote: ...
What I understand from your explanation on how make process a target is that: . It first do all of the expanding. Assuming the following make file:modules= a.o b.o c.o mylib.lib: $(modules) @echo starting... $(foreach n, $(modules), $(shell $(AR) -qur $@ $(n))) Make first expanding it to something such as this: modules= a.o b.o c.o mylib.lib: a.o b.o c.o @echo starting... $(AR) -qur $@ a.o $(AR) -qur $@ b.o $(AR) -qur $@ c.o
No. The the expansion of the $(shell) function is the output of the specified command, so all the $(AR) commands are being invoked while make is doing its expansion. Philip Guenther _______________________________________________ Help-make mailing list [email protected] http://lists.gnu.org/mailman/listinfo/help-make
