On Wed, 16 Aug 2006, Martin Gaarde Lund wrote:
Im working on a makefile which includes submakefiles which defines various
targets and variables. This affects my target definitions in a unfortunate
way.
I have summarized my problem in the following example makefile:
ERRORFILE = $(PROJECT).err
PROJECT = project
test.o:
armcc test.c -o test.o --errors $(ERRORFILE)
PROJECT = project1
test1.o:
armcc test1.c -o test1.o --errors $(ERRORFILE)
clean:
rm *.o
From this example I would have expected make to assemble the following
target commands:
armcc test.c -o test.o --errors project.err
armcc test1.c -o test1.o --errors project1.err
But what i get is:
armcc test.c -o test.o --errors project1.err
armcc test1.c -o test1.o --errors project1.err
As it appears the same ERRORFILE applies to both commands.. I realize that
this is an effect of how make reads through the makefile in different
stages.
Is it possible to make a construction which works as I intended it to?
Please note that I can not depend on the target rule for defining my error
output.
Any input will be appreciated, thanks.
/Martin
P.S. Im using GNU Make 3.81 built for i686-pc-mingw32
gmake is performing as expected. In rule commands (or whatever the term is),
the last definition in the makefile (or set of makefiles) is the one which
always wins.
You can perform it with per-target definitions:
ERRORFILE = $(PROJECT).err
test.o: PROJECT = project
armcc test.c -o test.o --errors $(ERRORFILE)
test1.o: PROJECT = project1
armcc test1.c -o test1.o --errors $(ERRORFILE)
clean:
rm *.o
Thanks,
Lee
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