Aditya Kher wrote:
Use target specific variables:
$ cat Makefile
FOO := whatever
.PHONY : all
all : target_1 target_2 target_3
target_1 : FOO := foo # override FOO for this target
target_2 : FOO := bar # override FOO for this target
target_% : ; @echo "cd ${FOO} && ls"
$ make
cd foo && ls
cd bar && ls
cd whatever && ls
Note that you have to put cd and ls on the same line, because each
rule line is
executed by another invocation of shell, so the effect of cd in the
previous
line is lost.
cool . this works but playing devils advocate...
why cant Make allow me something like this (gives error) ?
target_1 : FOO := foo # override FOO for this target
; @echo "cd ${FOO} && ls"
target_1 : FOO := foo is variable assignment's syntax, not rule's. Probably this
is the way make's parser works.
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