I'm trying to use a variable as a target without much luck. My makefile contains:
.PHONY = foobar foobar : a = foo foobar : b = bar c=$(a)$(b) $(c) : echo $(c) When I invoke
make foobar
... it returns: make: *** No rule to make target `foobar'. Stop. However it works if I replace the variable definition "c=$(a)$(b)" with "c=foobar": .PHONY = foobar foobar : a = foo foobar : b = bar c=foobar $(c) : echo $(c) Now I invoke
make foobar
... it returns: echo foobar foobar Why isn't it working when I use the variable $(c) as a target? I'm using GNU Make 3.80 for i686-pc-cygwin. thx, --Brendan
_______________________________________________ Help-make mailing list [email protected] http://lists.gnu.org/mailman/listinfo/help-make
