Hi,
I'm trying to write a makefile that has the following features:
1. Generates the list of files to build from a source and its designated
sub-directories
2. Builds the object and executable in an object directory (with required
subdirs)
3. Automatically creates .d dependency files using the approach recommended in
the make doco.
However if I touch one of the source files or add a new file to the source
directory, the system tries to build an executable named 'Makefile'. (It looks
like this occurs when the source files are newer than the Makefile).
I have make version 3.80.
Here's my Makefile. What am I doing wrong?
Thanks in advance.
Dushara
##############################################################################
# CONFIGURATION #
##############################################################################
# root directory of sources
SRC = src
# include directory
INC = inc
# root directory of objects
OBJ = obj
# list all subdirectories to build within src
SUB = sub1 sub2
##############################################################################
# TOOLS #
##############################################################################
CPP = gcc
CC = gcc
LD = gcc
RM = rm
##############################################################################
# Make a list of all the C sources to be built
CSRC = $(foreach DIR, . $(SUB), $(wildcard $(SRC)/$(DIR)/*.c))
COBJ = $(CSRC:$(SRC)/%.c=$(OBJ)/%.o)
CDEP = $(CSRC:$(SRC)/%.c=$(OBJ)/%.d)
all: $(COBJ)
@echo $@
clean:
@$(RM) -f $(COBJ)
@$(RM) -f $(CDEP)
# rule to build dependencies files for C source files
%.d: $(@:$(OBJ)/%.d=$(SRC)/%.c)
@echo $@
@$(CPP) -MM -I $(INC) $(@:$(OBJ)/%.d=$(SRC)/%.c) -o [EMAIL PROTECTED]
@sed 's,\($(notdir $*)\)\.o[ :]*,$(dir $*)\1.o $@ : ,g' < [EMAIL PROTECTED]
> $@
@$(RM) [EMAIL PROTECTED]
# rule to build c objects
%.o: $(CSRC:$(OBJ)/%.o=$(SRC)/%.c)
touch $@
include $(CDEP)
##############################################################################
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