On 1/2/07, David Wuertele <[EMAIL PROTECTED]> wrote:
I want to include a makefile multiple times, and I each time I want it to define rules based on the current value of some variables. But I'm stymied by the fact that Make only interpolates variable values for command scripts when they are executed, not when they are defined.For example: Makefile -------- MY_VAR := one include variabletest.mk MY_VAR := two include variabletest.mk variabletest.mk --------------- $(MY_VAR): echo $(MY_VAR) > $(MY_VAR) all: $(MY_VAR) When I type "make", I expect it to do this: echo one > one echo two > two But the rules for "one" and "two" both contain $(MY_VAR), which isn't evaluated until execution time, and at that point MY_VAR contains "two". So all I see is this: echo two > two How can I make make do what I want?
You can use target-specific variables. Try adding this line to the top of variabletest.mk: $(MY_VAR): MY_VAR := $(MY_VAR) That sets the variable MY_VAR for the target $(MY_VAR) (eg: "one" or "two") to $(MY_VAR). Since it's using := here, it won't be affected by future changes to MY_VAR. Also, note that make will build the first target it sees by default, which would be "one" in your example. You probably want to put an empty "all" target at the top of the Makefile so make will always build all by default: all: MY_VAR := one include ... etc -Mike _______________________________________________ Help-make mailing list [email protected] http://lists.gnu.org/mailman/listinfo/help-make
