The testcase below is a demonstration of a problem I've got with a much
larger build system with which I would like to start using parallel
builds. In the example below, the ok and the bad targets are essentially
the same, but the bad target uses a variable to invoke make. Why does
this variable cause a warning as shown below and how can I fix this? I'm
trying to avoid a huge rewrite by keeping the variables. The manual
indicates that $(MAKE) should be prefixed with a +, but this just causes
make to error out with:
/bin/sh: line 1: +make: command not found
Occurs in make 1.79.1 and 3.81. Perhaps there is a better way in make to
store common code, ie other than using it in a variable?
Thanks
William
#Makefile
TARGETS=one two
TARGETS_OLD=$(TARGETS:=.ok)
TARGETS_NEW=$(TARGETS:=.bad)
ok: $(TARGETS_OLD)
bad: $(TARGETS_NEW)
common_stuff = @echo bad $*; $(MAKE) $*.xtest
%.ok:
@echo ok $*
$(MAKE) $*.xtest
%.bad:
$(common_stuff);
%.xtest:
echo testing $*
Output:
$ make -s -j2 ok
ok one
ok two
testing one
testing two
$ make -s -j2 bad
bad one
bad two
make[1]: warning: jobserver unavailable: using -j1. Add `+' to parent
make rule.
make[1]: warning: jobserver unavailable: using -j1. Add `+' to parent
make rule.
testing one
testing two
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