Hello,
I have a simple Makefile which builds an executable using a pattern
rule. When the target it built, make automatically removes the object
files generated during the build process. How can I stop this? I've
played around with having multiple targets and objects, and this
behavior is robust. Also, changing the $(RM) variable has no effect.
Here is a sample Makefile which reproduces the problem:
-----------
all : hello.x
%.x: %.o
gcc $< -o $@
%.o: %.c
gcc -c $<
-----------
And the output:
--------------
gcc -c hello.c
gcc hello.o -o hello.x
rm hello.o
--------------
If I use the following Makefile instead:
-----------
hello.x: hello.o
gcc $< -o $@
%.o: %.c
gcc -c $<
-----------
Then I get:
-----------
gcc -c hello.c
gcc hello.o -o hello.x
-----------
What gives?
Any help would be appreciated. I am using GNU Make 3.81.
Thanks,
-Adam
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