Paul Smith writes:
I didn't think this work, and I was right. If I recall correctly, GNU
make invokes a new shell process for each line, so setting variables
won't work.
That problem is easily enough solved:
%.o : %.c
VAR=foo $(compile_c)
D'oh. I had not considered the simple idea :) I think this is the best way.
Target/Rule-specific variables won't work either, as I've got a mix of
C and C++ files so the variable only gets set once (when the Makefile
is parsed).
From this comment I'm not sure you understand how target specific
variables really work.
I was alluding to this part of the manual :
"Be aware that a given prerequisite will only be built once per invocation
of make, at most. If the same file is a prerequisite of multiple targets,
and each of those targets has a different value for the same target-specific
variable, then the first target to be built will cause that prerequisite to
be built and the prerequisite will inherit the target-specific value from
the first target."
I tried this and I appeared to hit this problem, the C++ rule was being used
to compile the C file. It's possible that I was seeing some other snafu ..
However, perhaps a simpler way to go is constructed variables. For
example:
<snip>
That's neat. I'll try that one as well.
Thank you very much for your help.
Brendan
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