On Wed, Jun 4, 2008 at 6:50 AM, John Graham-Cumming <[EMAIL PROTECTED]> wrote:
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>
> Peng Yu wrote:
> | For a file named as abc+=.cc, how do I refer to such name in Makefile?
> | I tried to abc\+\=.cc, but it seems not working.
>
> GNU Make's escaping rules won't help you there (see
> http://www.cmcrossroads.com/content/view/8442/120/) but you can just
> define a variable to contain the equals sign and use it to hide the =
> from the parser.
>
> e.g.
>
> e := =
>
> abc+$e.cc: ; @echo Making $@
>
> Or if you really want to do something wild you can define a variable
> called = which expands to =
>
> e := =
> $e := =
>
> abc+$=def: ; @echo Making $@

Actually, I'm using g++'s -MM option to automatically generate the
rules. The above technique is not support by gcc. And it seems not
convenient to be handled by gcc. I'm wondering if gmake (or in
general, make) can make some changes on the way these special
characters are handled. So that I can use g++'s -MM options for
arbitrary filename.

Thanks,
Peng


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