>> So, I'm looking for an idea to compile twice the same program (with the
>> same .o) with different option.
>
> You could use as command line variable (see Overriding Variables in
> the make manual). Suppose you compile with this rule:
>
> toto.o: toto.c
> $(COMPILER) $(MY_OPT) toto.c -ouput toto.o
>
> Then from the command line you can call it with either:
> make MY_OPT=-fprofile-generate
> or:
> make MY_OPT=-fprofile-use
> or nothing at all:
> make
>
> If you do not specify MY_OPT, make will put a blank for $(MY_OPT). It
> will not complain that it is undefined (see -warn-undefined-variables
> in the make manual).
>
> Please ignore that I do not know how to compile C programs and that
> the -output switch is probably wrong. My point is to use MY_OPT as a
> command line variable to show you one way of doing what you want.
> There are other ways, but this is the first that comes to my mind.
=> no problem. In C, the output option is -o
Here is what I have done (actually, I have several .o to do, but this is
to explain the idea) :
____________________________________________________
CFLAGS = -Wall -O3 $(PROF_GEN_USE)
default:
rm -f *.o toto
make PROF_GEN_USE=-fprofile-use toto
profgen:
make PROF_GEN_USE=-fprofile-generate toto
./toto
toto: toto.c
gcc $(CFLAGS) $< -o $(@)
-------------------------------------------------------------------------------------------
It can easily be improved, of course. Anyway, thank you for the idea of
variable overwriting.
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