Hi All, Here is my Makefile script ------------------------------------------------------ my_src_dir := dir_a dir_b
define dir-to-vpath #X vpath %c $1 vpath %S $1 #Z endef ifdef my_src_dir cmd = $(foreach dir,$(my_src_dir),$(call dir-to-vpath,$(dir))) $(warning $(cmd)) $(eval $(cmd)) endif all: 1.c 2.c 3.S ------------------------------------------------------ $make -f z.mak z.mak:11: #X vpath %c dir_a vpath %S dir_a #Z #X vpath %c dir_b vpath %S dir_b #Z z.mak:12: *** missing `endif'. Stop. I can't see how `endif` is missed. Anybody can help me? BTW, are there options to force `make' to output variable expansions and eval commands to stdout device after it read Makefile, so that I can do some analysis and locate where is wrong? Best Regards ------------------------- PRC Oct 17, 2008 _______________________________________________ Help-make mailing list Help-make@gnu.org http://lists.gnu.org/mailman/listinfo/help-make
