Re: Convert nmake Makefile to GNU Makefile

Tue, 03 Mar 2009 13:56:26 -0800

Achugatla, Vijay K. (LNG-CON) wrote:

But I have a 100s of files in a directory. I can not give the names of all the files inside the Makefile.

Is there any option or directive available in GNU make that searches a directory and gets the names of all the files available in that and then store that in a variable?

Also any idea how to set a destination directory? I mean I want to store all the object files in a directory and the executable in another directory. How to achieve that?

I wrote the following makefile which does part of what you ask for people here at my office. It doesn't have support for an object directory, but that probably wouldn't be that hard to add. You should be able to modify this file to meet your needs. I really need to turn this into a two file solution with one file with all of the unchanging parts for inclusion in the other. This makefile is only written for .c and .cpp files currently, but you can follow the patterns below to add others.


#-*-Makefile-*-

# Generic makefile
#
# This makefile will compile all .cpp and .c files found in this
# directory and any subdirectories all into one executable named
# $TARGET. It will detect changes in source files as well as
# changes in the header files included by the source files.
TARGET=application

CFLAGS=-ggdb3

#
# STOP -- You shouldn't need to edit below this line.
#

.PHONY: clean all

all: depend $(TARGET)


CXXFLAGS=$(CFLAGS)

SRCS=$(shell find . -name "*.cpp" -or -name "*.c")
CXX_SRCS=$(filter %.cpp,$(SRCS))
C_SRCS=$(filter %.c,$(SRCS))
OBJS = $(CXX_SRCS:.cpp=.o) $(C_SRCS:.c=.o)


$(TARGET): $(OBJS)
    @echo " [LD]    " $@
    @$(LINK.cc) $^ $(LOADLIBES) $(LDLIBS) -o $@

clean:
    @rm -f $(TARGET) $(OBJS)

#
# Dependencies
#

depend .depend dep:
    @rm -f .depend

ifneq ($(CXX_SRCS),)
    @$(CXX) $(CXXFLAGS) $(CPPFLAGS) -M $(CXX_SRCS) >> .depend
endif
ifneq ($(C_SRCS),)
    @$(CC) $(CFLAGS) $(CPPFLAGS) -M $(C_SRCS) >> .depend
endif

# Include the dependency information here.
ifeq (.depend,$(wildcard .depend))
include .depend
endif


#
# implicit rules (Run "make -p" for more details)
#

# Built-in Variables (repeated here for convenience)
#
# COMPILE.cc = $(CXX) $(CXXFLAGS) $(CPPFLAGS) $(TARGET_ARCH) -c
# COMPILE.cpp = $(COMPILE.cc)
# COMPILE.c = $(CC) $(CFLAGS) $(CPPFLAGS) $(TARGET_ARCH) -c
# OUTPUT_OPTION = -o $@
# LINK.cc = $(CXX) $(CXXFLAGS) $(CPPFLAGS) $(LDFLAGS) $(TARGET_ARCH)

# Making the output a little nicer to look at for implicit rules.

%.o: %.cpp
    @echo " [CXX]    " $<
    @$(COMPILE.cpp) $(OUTPUT_OPTION) $<

%.o: %.c
    @echo " [CC]    " $<
    @$(COMPILE.c) $(OUTPUT_OPTION) $<

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