I'm having issues using defines in a Makefile.
The following makefile:
=====================
PROGRAMS = server client
.PHONY: all
all: $(PROGRAMS)
server_LIBS := priv protocol
client_LIBS := protocol
define PROGRAM_template
$(1):
cc $($(1)_LIBS) -o $$@
endef
$(foreach prog,$(PROGRAMS),$(eval $(call PROGRAM_template,$(prog))))
=====================
generates this output
cc priv protocol -o server
cc protocol -o client
yet the following file
=====================
PROGRAMS = server client
.PHONY: all
all: $(PROGRAMS)
client_LIBS := protocol
define PROGRAM_template
# The following line has moved inside the define
server_LIBS := priv protocol
$(1):
cc $($(1)_LIBS) -o $$@
endef
$(foreach prog,$(PROGRAMS),$(eval $(call PROGRAM_template,$(prog))))
=====================
generates this (unexpected) output
cc -o server
cc protocol -o client
Does anyone have an idea why it might be doing this?
My GNU Make version is 3.80
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