Hello, Suppose in Makefile1 PRODCTS := pa pb pa_SOURCES := pa1.c pa2.c pb_SOURCES := pb1.c pb2.c
In Makefile2(including Makefile1) OBJ_DIR := /obj How to get the following variables in Makefile2? pa_OBJS := /obj/pa1.o /obj/pa2.o pb_OBJS := /obj/pb1.o /obj/pb2.o The requirements are, - xx_OBJS can only be got from xx_SOURCES(e.g. by functions), can not be hard-coded in Makefile1 - Makefile2 should be common and no code change is needed while new products(pc, pd...) are added into PRODUCTS in Makefile1 I wrote the following code but it does not work, define OBJS_template $(1)_OBJS := $(addprefix $(OBJ_DIR)/,$(addsuffix .o, $(basename $(notdir $$($(1)_SOURCES))))) endef $(foreach p, $(PRODUCTS),$(eval $(call OBJS_template,$(p)))) Thanks pacia _______________________________________________ Help-make mailing list [email protected] http://lists.gnu.org/mailman/listinfo/help-make
