[Already sent off-list; I didn't notice that I wasn't spreading the word...]
---------- Forwarded message ---------- From: Philip Guenther <[email protected]> Date: Fri, Jun 19, 2009 at 10:38 PM Subject: Re: How to recompile only the changed files To: Kevin <[email protected]> On Fri, Jun 19, 2009 at 8:46 AM, Kevin <[email protected]> wrote: > > I have a question on how to recompile the changed files only without > compiling the untouched ones. > > The following is a "Makefile" that works well in Cygwin. The only thing is it > re-compiles everything when I typed in "make", even I didn't change anything > in SOURCES. > > My question is how to avoid recompiling the whole project. Maybe it needs > only a simple correction, but what it is? The problem is that your makefile violates rule #2 from here: http://make.paulandlesley.org/rules.html ---- Every non-.PHONY rule must update a file with the exact name of its target. Make sure every command script touches the file "$@"-- not "../$@", or "$(notdir $@)", but exactly $...@. That way you and GNU make always agree. ---- Here's the rule that violates that: > > .c.o: > @echo "Compiling $<" > $(GCC_COMPILER) $(COMPILER_FLAGS) $(EXTRA_COMPILER_FLAGS) $(INCLUDES) -c > $< -o obj/$(@F) So, when make decides to build foo.o from foo.c, it really ends up building obj/foo.o. So, the next time you run it, it looks for foo.o, doesn't find it, and rebuilds obj/foo.o again. There are a couple ways to solve this; I suggest you go read Paul's notes at http://make.paulandlesley.org/ and see what works for you. Philip Guenther _______________________________________________ Help-make mailing list [email protected] http://lists.gnu.org/mailman/listinfo/help-make
