On Fri, Jul 03, 2009 at 02:55:53PM +1000, [email protected] wrote:
> Could someone explain me the actual evaluation order of variables and
> how $, $$, $(value ), $(eval ), $(call ) and $(shell ) operate?
>
> Reading the info page of $(eval ) gave me the impression that it gets its
> argument, evaluates it once then parses the resulting text as makfile
> source (and interprets it). Obviously that's a rather naive assumption and
> make is doing something more sophisticated. I'd appreciate if someone
> could tell me what or at least directed me towards some docs (other than
> the source of make).
>
IMHO, there are three passes in the whole make process:
1. eval pass, in which evals are expanded.
In the first case, your makefile is expanded as:
all: foo
foo: Makefile
@echo "start"
@echo "shell is <" ">"
# error occurred above, because expansion of $(VAR) calls $(shell ...),
# which is an no-existent-command
@echo "end"
In the second case, your makefile is expanded as:
all: foo
foo: Makefile
@echo "start"
@echo "shell is <" $(shell no-existent-command) ">"
@echo "end"
2. substitution pass, in which variables (and ifdef, etc.) are expanded.
In the first case, your makefile is expanded as:
all: foo
foo: Makefile
@echo "start"
@echo "shell is <" ">"
@echo "end"
In the second case, your makefile is expanded as:
all: foo
foo: Makefile
@echo "start"
@echo "shell is <" ">"
#error generated in the above command while expanding $(shell ...)
@echo "end"
3. real make pass, in which targets are built consequently.
However, the above description is kind of oversimplified, e.g. target-
specific variables are not discussed.
Hope it helps.
-Cheng
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