All,
thanks for your help. I tried both versions, the version from Cheng an
this one. I decided to use Chengs suggestion, thus I'm not the only
developer in this project and I found Chengs version better
understandable for "non makefile specialists". But the other suggestions
works as well!
Thanks again for all your help.
Regards,
Christian
Paul Smith schrieb:
On Thu, 2009-09-10 at 14:50 +0200, Christian Rogsch wrote:
I have the following problem with a makefile: I want to compile files
with different compiler flags, based on the name of the file.
There are a number of ways to do this. One is target-specific
variables, as Cheng suggested.
Another is constructed variable names. Variable names in make can
consist of other variables. So you could do something like this:
foo.o_CFLAGS = -g
%.o : %.c
$(CC) $(CFLAGS) $($...@_cflags) -o $@ -c $<
The $($...@_cflags) (or, equivalently, $($(@)_CFLAGS)) expands to the value
contained in the variable named by concatenating the target ($@) with
the string _CFLAGS.
Personally I find this method the most aesthetically pleasing, mainly
because in my complex make environments I like to have all the "user
visible" makefile purely data-driven: they simply declare variables but
never need to declare rules. The rules are all created in some deeply
magical common makefiles set up for the project.
The final way to do it is with $(eval ...) but this is overkill for this
problem, 99% of the time.
--
Dipl.-Ing. Christian Rogsch
Bergische Universität Wuppertal
Fachbereich D, Abteilung Bauingenieurwesen
Lehr- und Forschungsgebiet Baustofftechnologie und Brandschutz
Pauluskirchstraße 7
Gebäude HF
Raum HF 24
42285 Wuppertal
Tel: +49 (0) 202 439 4241
Fax: +49 (0) 202 8 25 60
www.btbs.uni-wuppertal.de
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