Can you try to define an command variable, maybe you can use like this:
define echo-def
echo "common"
endef
override define echo-def
echo "common"
echo "I am override"
endef
all:
$(echo-def)
On 11 August 2010 15:42, Lynn Lin <lynn.xin....@gmail.com> wrote:
> All,
> is that possible we can override target (rules)? I know we can use
> :: to append target with multi rules.However I define a common
> makefile which define a target with rules and I want to override it in
> one makefile which include that common makefile
>
> for example :
> in common makefile:
>
> all:
> echo "common"
>
> in the other makefile which include that common makefile ,I want to
> override rules
> all:
> echo "I am override"
>
> when we run make all in makefile,it will run this two rules .I only
> want to run the override one
>
> Thanks
> Lynn
>
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> Help-make@gnu.org
> http://lists.gnu.org/mailman/listinfo/help-make
>
--
Best regards！
Thanks
Jiongliang Zhang
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