Hi,
I want to use GNU make in favour of Microsoft NMake and have been doing
some investigations on how to convert our existing makefiles. Here is a
summary of what I have discovered and tested so far:
NMAKE GNU MAKE
======= ==========
!MESSAGE hello world $(info hello world)
!ERROR message $(error message)
!INCLUDE filename include filename
$(MAKEDIR) $(CURDIR)
$(@D) $(@D:\=)
$(@F) $(@F)
$(@B) $(basename $(@F))
$(@R) $(basename $@)
$(var:find=replace) $(subst find,replace,$(var))
!IF "a" == "b" (also !=) ifeq (a, b)
(also ifneq)
... ...
!ELSE else
... ...
!ENDIF endif
!IF DEFINED(var) (also !DEFINED) ifdef var
(also ifndef)
... ...
!ELSE else
... ...
!ENDIF endif
!IF EXIST("filename") ifeq ($(wildcard filename),
filename) (NOTE: Case-sensitive!)
... ...
!ELSE else
... ...
!ENDIF endif
doit: define runit_cmd
@echo <<runit.cmd >nul ...$(1), $(2), $(3),...
...%1,%2,%3,... endef
<< doit:
@call runit.cmd x y z $(call runit_cmd, x, y, z)
Things I haven't found an alternative for yet:
1. Logical operations on !IF, e.g.:
!IF DEFINED(xyz) && ("a" == "b") || ("c" == "d")
2. Repeating a command for every dependency of a target, e.g.:
fred: a.adl b.adl c.adl
!nmake buildall MODULE=$** BUILDADL.MAK
Can anyone help me out on these two cases?
Thanks in advance,
Anjum.
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