Hi,
I have a little make puzzle that seems like it should have been done
before. I'm trying to write a makefile that builds for for multiple
architectures in the same source tree by directing the output to an object
directory dependent upon the architecture. So if I have the source tree
below
root
src
component1
component2
After building it looks like this for i386 and x86_64 architectures
root
src
build
i386
component1
component2
x86_64
component1
component2
The challenge I have is handling the auto generated dependency makefiles.
Each arch can have its own, so those files need to be in the build tree
with the object files. In the example below I'm using the example from the
make manual for generating prerequisites (changed to static pattern rule.)
$(OBJDIR) needs to be made before any target. For "regular" targets, all
that is necessary is to make $(OBJDIR) the first prerequisite of "all". But
for makefile targets, make executes their rule before anything else. Is
their some construction that I can use to get the target directory made for
the makefiles the same way I do the object files?
SRCDIR = hello
sources = hello.cpp
MAKEFILEDEPS = $(addprefix $(OBJDIR)/, $(sources:.cpp=.d))
MAKEFILES = $(MAKEFILEDEPS)
CPPOBJS = $(addprefix $(OBJDIR)/, $(sources:.cpp=.o))
OBJDIR = $(WORKDIR)/build/$(ARCH)/$(SRCDIR)
$(OBJDIR):
if [ ! -e $(OBJDIR) ]; then mkdir -p $(OBJDIR); fi
.PHONY: all clean
all: $(OBJDIR) hello
hello: $(OBJDIR)/hello.o
echo making $@
$(CXX) -o $@ $<
$(CPPOBJS) : $(OBJDIR)/%.o: %.cpp
# commands to execute (built-in):
echo making $@
$(COMPILE.cpp) $(OUTPUT_OPTION) $<
$(MAKEFILEDEPS): $(OBJDIR)/%.d: %.cpp
set -e; rm -f $@; \
$(CXX) -MM $(CPPFLAGS) $< > $...@.$$$$; \
sed 's,\($*\)\.o[ :]*,\1.o $@ : ,g' < $...@.$$$$ > $@; \
rm -f $...@.$$$$
clean:
$(RMDIR) $(OBJDIR)
# don't include the dependencies when cleaning
#ifneq (clean, $(findstring clean, $(MAKECMDGOALS)))
# Try to include dependency files.
sinclude $(MAKEFILEDEPS)
#endif
Thanks,
Chris_______________________________________________
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