I have a strange sitation (at least for me) in which make does not go after default goal.
Makefile:
-----
exec = myexec
include depends
include object_list
all: $(exec)
$(exec): $(objects)
depends:
for i in *.c ; do gcc -MM $$i ; done > depends
object_list:
echo objects = > object_list
for i in *.c ; do echo objects += `basename $$i .c`.o ; done >>
object_list
clean:
@-rm $(exec)
@-rm $(objects)
@-rm depends
@-rm object_list
.PHONY: clean
-----
execution:
-----
$ make
Makefile:3: depends: File not found
Makefile:4: object_list: File not found
echo objects = > object_list
for i in *.c ; do echo objects += `basename $i .c`.o ; done >> object_list
for i in *.c ; do gcc -MM $i ; done > depends
cc -c -o myexec.o myexec.c
-----
Why does make don't go like if 'make all' issued?
Thanks
Noel
er Envite
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