JeffS wrote:
Hi! I'm using GNU Make 3.80. In my Makefile, I use automatic
variable $@ to refer to the current target, as shown below.
| @echo current target is ... [$@]
ifeq ($@,sms)
@echo yep, they are equal
else
@echo no, they are not equal
endif
|
It seems that $@ expands to sms , as shown in the output below.
Output is:
|current target is ... [sms]
no, they are not equal
|
My question: since $@ (apparently) expands to sms , shouldn't the
"true" branch of the ifeq conditional be executed (with the
consequence that the output should read yep, they are equal)? [I am at
a loss as to why the output is no, they are not equal.]
Thank you for any advice you can provide.
The ifeq are evaluated during makefile parsing step they control what
make 'sees' in the makefile. $@ (and all automatic variables)
is only available in command script and commands evaluation is deferred
until second phase (that is not 100% correct see secondary expansion).
The analogy (not exact) is as you would expect C preprocesor macros
being evaluated during runtime.
If you do not understand what I'm talking about :-) see following
chapters of make manual:
3.9 How make Reads a Makefile
7. Conditional Parts of Makefile (first paragraph exactly explains why
it doesn't work)
10.5.3 Automatic Variables
Anyways to achieve what you want use if function instead i.e.:
comma=,
all: sms nosms
sms:
@echo current target is ... [$@]
@echo $(if $(filter-out xx,x$(subst $@,,sms)$(subst
sms,,$@)x),no$(comma) they are not equal,yep$(comma) they are equal)
nosms:
@echo current target is ... [$@]
@echo $(if $(filter-out xx,x$(subst $@,,sms)$(subst
sms,,$@)x),no$(comma) they are not equal,yep$(comma) they are equal)
note commas are argument separarors so thats why I had to escape them
with variable (another useful trick :-)
Thanks
Chris
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