>> Hmm, that's an interesting approach, but I still need to use the
>> -include directive, no?
>
> Yes, you still need the -include...
>
>> If I do, then my problem persists: .d files are created for each make
>> clean invocation
>
> ...but this won't happen if the .d files are not targets.
Yes, this seems to have resolved the problem.
My Makefile now looks like this:
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
$(OBJDIR)%.o: %.cpp | $(OBJDIR) $(BISON_HDRS)
$(CXX) $(CXXFLAGS) -c $< -o $@ -MMD -MP -MT '$(OBJDIR)$*.o'
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Thanks a lot,
Nick
--
=Do-
N.AND
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