On Sun, 2013-05-26 at 00:19 +0200, Riccardo Manfrin wrote:
> Hi list,
> I have the following main makefile:
>
> #Makefile
>
> include Makefile1
>
> all: $(MAKE_DEPS_ALL)
> @echo $(MAKE_DEPS_ALL)
>
> and Makefile1 file
>
> #Makefile1
>
> MAKE_DEPS_ALL+=mydep
>
> mydep:
> $(MAKE) -C /my/path
>
> Unfortunately, mydep dependency is not resolved. I see "mydep" when I
> print MAKE_DEPS_ALL, but the depencency is not looked up.
Your example works for me. Are you sure you used EXACTLY this example
to reproduce the problem? I'll bet you had something like this instead:
all: $(MAKE_DEPS_ALL)
@echo $(MAKE_DEPS_ALL)
include Makefile1
Rule targets and prerequisites are expanded immediately when the
makefile is parsed, so changes to variables after they appear in targets
and prerequisites are not reflected there.
In this particular case, though, you don't need to create a variable.
Just add the prerequisite as you go:
all: mydep
mydep:
$(MAKE) -C /my/path
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