I am intrigued by the behaviour of make with this makefile:
t1: $(info t1 deps)
echo Done $@
t2:
echo Done $@
$ make t2
t1 deps
Done t2
$
Make unnecessarily computes the dependencies for target t1 but t1 is not a
target in this scenario.
I looked at the bug list in savannah but I did not find anything similar.
Should I open an enhancement request?
Thanks,
Martin
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