Hi,
I have 2 problems with a Makefile that I have crafted. The first one is that
I'm doing this:
# Would need to make those variable recursive if debug target redefine the dir
vars.
OBJS = $(SRCS:%.cpp=%.o)
DEPS = $(SRCS:%.cpp=$(DEPDIR)%.depends)
CPPFLAGS = -DNDEBUG -DBASE_VERSION
CXXFLAGS = -std=gnu++11 -pthread -march=native -Wall -O3
LDFLAGS = -pthread -Lbase
LIBS := -lbase $(shell pkg-config --libs libxml-2.0) $(shell pkg-config --libs
libcrypto)
SUBDIR_TARG := all
.PHONY : clean all subdirs $(SUBDIRS)
# 'all' is the default target because it is the target of the first declared
target.
all : $(TARGET)
subdirs: $(SUBDIRS)
#
# Possible additions to the debug target
# - Use different directories for storing intermediate files so they can
# coexist with the release ones
# - Change target name
#
debug : CFLAGS = -std=gnu++11 -pthread -Wall -g -O0
debug : CXXFLAGS = -std=gnu++11 -pthread -Wall -g -O0
debug : CPPFLAGS = -DTRLDEBUG
debug : SUBDIR_TARG := debug
debug : all
$(SUBDIRS):
$(MAKE) -C $@ $(SUBDIR_TARG)
$(TARGET) : $(SUBDIRS) $(OBJS)
$(CXX) $(LDFLAGS) -o $@ $(OBJS) $(LIBS)
$(DEPDIR) :
mkdir $(DEPDIR)
# pattern rules
# SHELL switches:
# e: to exit immediatly if gcc fails
# c: The script to execute is provided as a string argument with the command.
# - $* expends to '%' from the rule (In make terminology, the stem).
# - The sed script triple single quote is tricky to understand. It is not
allowed in
# shell scripting to have a single quote between 2 single quotes so what is
done instead
# is to close the quote started from the first line, add an escaped single
quote
# reopen the initial quote.
# - 3rd line is for testing that the sed output file is not empty and delete it
# otherwise.
# - '!' is used as the sed command delimiter instead of the usual '/'. This is
because we expect
# the '/' char to appear in directory component of the filenames.
$(DEPDIR)%.depends: %.cpp $(DEPDIR)
$(SHELL) -ec '$(CXX) -MM $(INCLUDES) $(CPPFLAGS) $(CXXFLAGS) $< \
| sed '\''s!\($*\)\.o[ :]*!\1.o $@ : !g'\'' > $@; \
[ -s $@ ] || rm -f $@'
%.o: %.cpp
$(CXX) $(CXXFLAGS) $(INCLUDES) $(CPPFLAGS) -c $< -o $*.o
clean :
-rm -rf $(DEPDIR) $(TARGET) *.o
make -C base clean
# rules defining dependencies and using commands defined in pattern rules are
included here.
-include $(DEPS)
my debug specific variables are expanded correctly for the targets $(TARGET)
and %.o but are ignored for $(DEPDIR)%.depends. This not a very big deal but it
could lead some inaccuracies if some headers files are conditionally included
based on some defines included in $(CPPFLAGS).
I kinda understand that my problem is related to the 2 make read phases but I
do not know how reformulate my makefile to deal with it.
My second problem is that I am trying to reuse my implicit rules for a second
target ie:
client_test : TARGET = client_test
client_test : SRCS = ClientBase.cpp client.cpp clientfsm.cpp http_clientfsm.cpp
\
client_test.cpp
This doesn't work at all.
OBJS = $(SRCS:%.cpp=%.o)
DEPS = $(SRCS:%.cpp=$(DEPDIR)%.depends)
expansion do not consider at all the target specific values.
prerequisite secondary expansion seems to be more what I should use but I am
not sure this is applicable since OBJS variable is used also in the rule recipe.
Links to complex makefile examples and/or templates that contains stuff similar
that I am trying to accomplished are welcome.
Thank you for your time.
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