On Sat, 2021-05-22 at 21:13 +0900, Masahiro Yamada wrote:
> - 'make vmlinux modules' builds __common with
> BUILDING_VMLINUX=y and BUILDING_MODULES=y
>
> I know the example above does not work like that.
This is the part that won't work; the rest works fine AFAICS.
The problem is a common misconception, that make targets are like
functions or subroutines. They are not: they are recipes to build
files. Even .PHONY targets.
This means that once a target is built one time in a makefile it will
_never be built again_ (in that run of make). So, unlike a function or
a subroutine you can't "call" a target multiple times in a makefile.
So you cannot collect a "common part" of a recipe into a separate
target that is depended on by multiple other targets, if you need that
common part to be run multiple times. It just doesn't work like that.
You could put the common part into a variable and then use that
variable in all the targets, something like this:
define __common
@echo BUILDING_VMLINUX is $(BUILDING_VMLINUX)
@echo
BUILDING_MODULES is $(BUILDING_MODULES)
[ common build rules,
which internally uses
BUILDING_{VMLINUX,MODULES} conditionals
]
endef
.PHONY: vmlinux modules
vmlinux: export BUILDING_VMLINUX=y
modules: export BUILDING_MODULES=y
vmlinux modules:
$(__common)
