Given a Makefile:
debug:
echo "$(foo)"
echo "$(subst $,$$,$(foo))"
echo "$(subst $$,%,$(foo))"and given the make command: $ foo='FOO$BAR' make -f /tmp/Makefile How can I get make to not try to resolve the $ in the value as it seems to be doing for all of the echos in the debug target: $ foo='FOO$BAR' make -f /tmp/Makefile echo "FOOAR" FOOAR echo "FOOAR" FOOAR echo "FOOAR" FOOAR I suppose the $(subst) attempts are too late and $(foo) has it's $B resolved as the variable is expanded before $(subst) can even get a chance to try to escape it. An obvious solution is to escape the $ in the caller's foo assignment before calling make, but that is asking the caller to do something surprising simply to appease make. Not nice to do. Any solutions other than asking the caller to alter their normal behaviour? Cheers, b.
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