Hi,
I'm trying to follow Paul’s third rule of makefiles
(http://make.mad-scientist.net/papers/rules-of-makefiles/#rule3).
However, I find it difficult to follow if the target and source use
the same file name.
For example, say I have a couple files that need to be deploy to a server:
src/app_a/etc/app_a.config.tpl
src/app_a/usr/bin/app_a
src/app_b/etc/app_b.config.tpl
src/app_b/usr/bin/app_b
They should be built as
build/etc/app_{a,b}.config
build/usr/bin/app_{a,b}
So they can be easily synced to the server.
*.tpl files are rendered with a template engine, and bin files are
just bash scripts that should be copied over.
I tried this makefile (src/../Makefile):
```
VPATH = ../src/app_a:../src/app_b
%: %.tpl data.json
render --data data.json $< $@
%: %
cp $< $@
```
and make is run in build/ with:
make -f ../Makefile etc/app_a.config usr/bin/app_b
It can successfully build app_a.config, but for usr/bin/app_b, it
complains about circular dependency, which is understandable.
I wonder if it's possible to solve this circular dependency? Like
somehow force make to only consider VPATH for prerequisites and not
targets?
One solution I can think of is to break rule #3:
```
VPATH = src/app_a:src/app_b
build/%: %.tpl data.json
render --data data.json $< $@
build/%: %
cp $< $@
```
and run make from the top directory:
make -f Makefile build/etc/app_a.config build/usr/bin/app_b
But this doesn't feel elegant, and it becomes complicated once I need
to support multi-arch (build/{x64,arm64}/..).
Would be grateful if someone could shed some light.
Regards,
Glen
