On 2022-06-23 02:26, Ming Cheng wrote:
> Hi Help desk,
>
> I have a xxx.mk file.
GNU Make will not read a xxx.mk file unless you run
make -f xxx.mk
; it looks for Makefile by default. What you have there is likely a make
include file. Some other makefile is including it.
Some people write build systems in which you define some xxx.mk file
in every directory, and in that file you just declare what is to be
pulled into the build by defining some variables.
Make is very flexible with variables; it can operate indirectly
on variable names as strings. A given build system written in GNU Make
can have a special meaning in a situation like this:
modules := abc
abc_type := static_library
abc_target := libabc.a
Make treats this as three ordinary variable assignments. However,
of course, it is a fact that the characters "abc" occur in
"abc_type". This fact can be exploited in a computed variable
name expansion:
$(abc_type) # ordinary expansion, produces static_library
$($(modules)_type) # also produces static_library !
First $($(modules)_type) becomes $(abc_type) via expansion of
$(modules) and then that expands again.
I see that modules is pluralized, suggesting that you can do
this:
modules := abc def
so then, say that we would like to map this to the corresponding targets
$(foreach m, $(modules), $($(m)_target))
Or get the type of the first module:
$($(firstword $(modules))_type)
Your build system almost certainly contains these kinds of calculations.
The typical pattern is:
- for each build directory:
- first, clear all the special variables like "modules" or whatever to empty
values
- include the xxx.mk file,
- examine the values of the special variables it has assigned and update
other variables and possibly generate rules
For instance, all the targets that are implied in the variable definitions
might be added to some internal "all_targets" variable.
all_targets += $(foreach m, $(modules), $($(m)_target))
This might then be mentioned in a clean rule:
clean:
$(rm) ... $(all_targets) ..
