Dear all,
There is something about variable expansion that I do not understandf.
Consider the following Makefile:
all: $(PROGRAMS)
define BUILD_MACRO
$(1): $$($$(basename $$(notdir $(1)))_OBJECTS:=.o)
@echo Building $$@ from $$^
endef # BUILD_MACRO
PROGRAMS = tools/prog.exe
prog_OBJECTS = progmod1 progmod2
$(foreach PROGRAM, $(PROGRAMS),\
$(eval $(call BUILD_MACRO,$(PROGRAM))))
If progmod1.o and progmod2.o exist, then running `make tools/prog.exe` displays:
Building tools/prog.exe from progmod1.o progmod2.o
Which is what I expect.
However, if prog_OBJECTS is defined after the call to foreach rather
than before, then the same command ran in the same context says:
Building tools/prog.exe from
In other words the evaluated list of prerequisites is empty and I am
wondering why this is so and whether there would be a way to defiine
BUILD_MACRO so that therelative positions of its invocation andthe
definition of the _OBJECTS variables does not matter.
Many thanks in advance for your lights,
Sébastien.
