CALL FOR PARTICIPATION
Sixth ACM-IEEE International Conference on
Formal Methods and Models for Codesign
(MEMOCODE)
co-located with DAC
June 5-7, 2008, Anaheim, CA, USA
http://memocode-conference.com
http://svl1.cs.pdx.edu/memocode08
The sixth MEMOCODE conference will gather researchers and
practitioners who design modern hardware/software systems. MEMOCODE's
mission is to consider new formal and systematic techniques for the
design of dependable hardware/software systems. Many new languages,
abstractions, refinement, and analysis techniques have already proven
to provide a sound methodological basis for high-level modeling,
design, and development of hardware and software systems, including
the adaptation and re-use of existing components.
Keynotes:
=========
o Bart Kienhuis.
"Programming multicores with Kahn Process Networks;
a smart choice?"
o Tevfik Bultan.
"Infinite State Model Checking with Arithmetic Constraints"
Panel:
======
o Anthony Chun (Intel), Marcello Coppola (STMicroelectronics),
Nikil Dutt (UCI), Radu Marculescu (CMU),
Drew Wingard (Sonics Inc.)
"Methodologies and Tools for On-Chip Communication Design:
Trends and Challenges".
Tutorial:
=========
o Arvind and Rishiyur Nikhil.
"Hands-on Introduction to Bluespec SystemVerilog (BSV)"
Technical Presentations:
========================
-----------------------
* Formal Verification *
-----------------------
o Omid Sarbishei, Bijan Alizadeh and Masahiro Fujita.
"Arithmetic Circuits Verification without Looking for
Internal Equivalences"
o Christophe Jacquet, Frédéric Boulanger and Dominique Marcadet.
"From Data to Events: Checking Properties on the Control
of a System"
o Graziano Pravadelli, Luigi Di Guglielmo and Franco Fummi.
"Vacuity Analysis by Fault Simulation"
---------------------------------------------
* Semantics of System Description Languages *
---------------------------------------------
o Subash Shankar and Masahiro Fujita.
"Rule-Based Approaches for Equivalence Checking of SpecC
programs"
o Nalini Vasudevan and Stephen A. Edwards.
"Static Deadlock Detection for the SHIM Concurrent Language"
o Claude Helmstetter and Olivier Ponsini.
"A Comparison of Two SystemC/TLM Semantics for Formal
Verification"
---------------------------------------------
* Tools and Techniques for Processor Design *
---------------------------------------------
o Steve Haynal, Timothy Kam, Michael Kishinevsky, Emily
Shriver and Xinning Wang.
"A SystemVerilog Rewriting System for RTL Abstraction"
o Michael Katelman, Jose Meseguer and Santiago Escobar.
"Directed-Logical Testing for Functional Verification of
Microprocessors"
o Daniel Grund and Jan Reineke.
"Estimating the Performance of Cache Replacement Policies"
-----------------------
* Design Case Studies *
-----------------------
o Kermin Fleming, Chun-Chieh Lin, Nirav Dave, Jamey Hicks,
Gopal Raghavan and Arvind Arvind.
"H.264 Decoding: A Case Study in Late Design-Cycle Changes"
o Eyad Alkassar, Peter Boehm and Steffen Knapp.
"Correctness of a Fault-Tolerant Real-Time Scheduler
Algorithm and its Hardware Implementation"
o Venkatram Vishwanath, Lenore Zuck and Jason Leigh.
"Specification and Verification of LambdaRAM: A
Wide-area Distributed Cache for High Performance
Computing"
---------------------------------------------
* Models of Computation *
---------------------------------------------
o Christian Zebelein, Joachim Falk and Christian Haubelt.
"Classification of General Data Flow Actors into known
Models of Computation"
o Bijoy A. Jose, Sandeep K. Shukla, Hiren D. Patel and
Jean-Pierre Talpin.
"On the Automatic Inference of Synchronization Logic for
Multi-threaded Software Synthesis from Polychronous
Specifications"
o Yue Ma, Jean-Pierre Talpin and Thierry Gautier.
"Virtual prototyping AADL architectures in a
polychronous model of computation"
---------------------------------------------
* Posters *
---------------------------------------------
o G. Hoover, F. Brewer and C. Gill.
"Latency-Insensitive Implementation of Hardware/Software
Interfaces"
o R. Mateescu and E. Oudot.
"Efficient On-the-Fly Equivalence Checking using Boolean
Equation Systems"
o Katell Morin-Allory, Yann Oddos and Dominique Borrione.
"Horus: A tool for Assertion-Based Verification and
on-line testing"
---------------------------------------------
* Co-Design Contest Presentations *
---------------------------------------------
========
CHAIRS
========
General Chairs
Forrest Brewer, UC Santa Barbara, USA
Rajesh Gupta, UC San Diego, USA
Program Chairs
Stephen A. Edwards, Columbia, USA
Klaus Schneider, Kaiserslautern, Germany
Publicity Chair
Fei Xie, Portland State, USA
Panel Chair
Luca Carloni, Columbia, USA
Industry Chair
Arvind, MIT, USA
Local Arrangements
Forrest Brewer, UC Santa Barbara, USA
TECHNICAL PROGRAM COMMITTEE
Arvind, MIT, USA
Twan Basten, Eindhoven, Netherlands
Forrest Brewer, UC Santa Barbara, USA
Tevfik Bultan, UC Santa Barbara, USA
Luca Carloni, Columbia, USA
Robert de Simone, INRIA, France
Stephen A. Edwards, Columbia, USA
Masahiro Fujita, Tokyo, Japan
Franco Fummi, Verona, Italy
Ganesh Gopalakrishnan, Utah, USA
Rajesh Gupta, UC San Diego, USA
Connie Heitmeyer, NRL, USA
James Hoe, CMU, USA
Ahmed Jerraya, CEA, France
Thomas Kropf, Bosch, Germany
Luciano Lavagno, Politecnico di Torino, Italy
Elizabeth Leonard, NRL, USA
John O'Leary, Intel, USA
Zebo Peng, Linkoping, Sweden
Carl Pixley, Synopsys, USA
Patrick Schaumont, Virginia Tech, USA
Klaus Schneider, Kaiserslautern, Germany
Sandeep Shukla, Virginia Tech, USA
R. K. Shyamasundar, TIFR, India
Jean-Pierre Talpin, INRIA, France
P. S. Thiagarajan, Singapore
Reinhard Wilhelm, Saarland University, Germany
Fei Xie, Portland State, USA
-------------------------------------------------------------------------
This SF.net email is sponsored by the 2008 JavaOne(SM) Conference
Don't miss this year's exciting event. There's still time to save $100.
Use priority code J8TL2D2.
http://ad.doubleclick.net/clk;198757673;13503038;p?http://java.sun.com/javaone
_______________________________________________
hol-info mailing list
[email protected]
https://lists.sourceforge.net/lists/listinfo/hol-info
