Hi, this is my first post on this mailing list -- I just found hwloc and it seems like a useful tool for my research. As an initial test I ran hwloc-info on our 8 socket Opteron 8356 system (32 cores), the full results are attached below. The node information is correct, as is the level 2 cache information. However, the L1 cache size is wrong and the L3 cache is in fact shared between each set of 4 cores (its size is correct though). I couldn't find any in-depth description on how hwloc tries to determine this information, so I'm not sure if this behaviour is caused by our system lacking some required feature or by a problem in hwloc. If you need more information I'll be happy to provide it.
Best regards, Peter [petert@m01 ~]$ hwloc/inst/bin/hwloc-info --version hwloc-info 0.9.1a1 [petert@m01 ~]$ hwloc/inst/bin/hwloc-info - System(63GB) Node#0(8061MB) + Socket#1 L3(2048KB) + L2(512KB) + L1(512KB) + Core#0 + P#0 L3(2048KB) + L2(512KB) + L1(512KB) + Core#1 + P#1 L3(2048KB) + L2(512KB) + L1(512KB) + Core#2 + P#2 L3(2048KB) + L2(512KB) + L1(512KB) + Core#3 + P#3 Node#1(8080MB) + Socket#2 L3(2048KB) + L2(512KB) + L1(512KB) + Core#0 + P#4 L3(2048KB) + L2(512KB) + L1(512KB) + Core#1 + P#5 L3(2048KB) + L2(512KB) + L1(512KB) + Core#2 + P#6 L3(2048KB) + L2(512KB) + L1(512KB) + Core#3 + P#7 Node#2(8080MB) + Socket#3 L3(2048KB) + L2(512KB) + L1(512KB) + Core#0 + P#8 L3(2048KB) + L2(512KB) + L1(512KB) + Core#1 + P#9 L3(2048KB) + L2(512KB) + L1(512KB) + Core#2 + P#10 L3(2048KB) + L2(512KB) + L1(512KB) + Core#3 + P#11 Node#3(8080MB) + Socket#4 L3(2048KB) + L2(512KB) + L1(512KB) + Core#0 + P#12 L3(2048KB) + L2(512KB) + L1(512KB) + Core#1 + P#13 L3(2048KB) + L2(512KB) + L1(512KB) + Core#2 + P#14 L3(2048KB) + L2(512KB) + L1(512KB) + Core#3 + P#15 Node#4(8080MB) + Socket#5 L3(2048KB) + L2(512KB) + L1(512KB) + Core#0 + P#16 L3(2048KB) + L2(512KB) + L1(512KB) + Core#1 + P#17 L3(2048KB) + L2(512KB) + L1(512KB) + Core#2 + P#18 L3(2048KB) + L2(512KB) + L1(512KB) + Core#3 + P#19 Node#5(8080MB) + Socket#6 L3(2048KB) + L2(512KB) + L1(512KB) + Core#0 + P#20 L3(2048KB) + L2(512KB) + L1(512KB) + Core#1 + P#21 L3(2048KB) + L2(512KB) + L1(512KB) + Core#2 + P#22 L3(2048KB) + L2(512KB) + L1(512KB) + Core#3 + P#23 Node#6(8080MB) + Socket#7 L3(2048KB) + L2(512KB) + L1(512KB) + Core#0 + P#24 L3(2048KB) + L2(512KB) + L1(512KB) + Core#1 + P#25 L3(2048KB) + L2(512KB) + L1(512KB) + Core#2 + P#26 L3(2048KB) + L2(512KB) + L1(512KB) + Core#3 + P#27 Node#7(8080MB) + Socket#8 L3(2048KB) + L2(512KB) + L1(512KB) + Core#0 + P#28 L3(2048KB) + L2(512KB) + L1(512KB) + Core#1 + P#29 L3(2048KB) + L2(512KB) + L1(512KB) + Core#2 + P#30 L3(2048KB) + L2(512KB) + L1(512KB) + Core#3 + P#31
