Sorry,
I forgot to tell you these code block is inside a parallel OpenMP region.
This is the complete code:
#pragma omp parallel num_threads(6)
{
int tid = omp_get_thread_num();
hwloc_obj_t core = hwloc_get_obj_by_type(topology, HWLOC_OBJ_CORE, tid);
hwloc_cpuset_t set = hwloc_bitmap_dup(core->cpuset);
hwloc_bitmap_singlify(set);
hwloc_set_cpubind(topology, set, HWLOC_CPUBIND_THREAD);
hwloc_bitmap_free(set);
}
and other code block is:
#pragma omp parallel num_threads(6)
{
int tid = omp_get_thread_num();
hwloc_obj_t core = hwloc_get_obj_by_type(topology, HWLOC_OBJ_PU, tid);
hwloc_cpuset_t set = hwloc_bitmap_dup(core->cpuset);
hwloc_bitmap_singlify(set);
hwloc_set_cpubind(topology, set, HWLOC_CPUBIND_THREAD);
hwloc_bitmap_free(set);
}
The goal is physically bind threads as near as possible, one thread per
core. Since core ids reported on hwloc-hello.c are not consecutive and not
exclusive, I suppose is better and more sure to use PU id. Or not?
2011/7/29 Samuel Thibault <samuel.thiba...@inria.fr>
> Gabriele Fatigati, le Fri 29 Jul 2011 13:24:17 +0200, a écrit :
> > yhanks for yout quick reply!
> >
> > But i have a litte doubt. in a non SMT machine, Is it better use this:
> >
> > hwloc_obj_t core = hwloc_get_obj_by_type(topology, HWLOC_OBJ_CORE, tid);
> > hwloc_cpuset_t set = hwloc_bitmap_dup(core->cpuset);
> > hwloc_bitmap_singlify(set);
> > hwloc_set_cpubind(topology, set, HWLOC_CPUBIND_THREAD);
> >
> > or:
> >
> > hwloc_obj_t core = hwloc_get_obj_by_type(topology, HWLOC_OBJ_PU, tid);
> > hwloc_cpuset_t set = hwloc_bitmap_dup(core->cpuset);
> > hwloc_bitmap_singlify(set);
> > hwloc_set_cpubind(topology, set, HWLOC_CPUBIND_THREAD);
> >
> > because work in the same way( i suppose).
>
> They'll both work about the same way on SMT too, since in the end it'll
> pick up only one thread. Whether you want to assign threads to cores or
> threads then depends on your application: do you want to let its threads
> share a core or not.
>
> Samuel
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> hwloc-us...@open-mpi.org
> http://www.open-mpi.org/mailman/listinfo.cgi/hwloc-users
>
--
Ing. Gabriele Fatigati
Parallel programmer
CINECA Systems & Tecnologies Department
Supercomputing Group
Via Magnanelli 6/3, Casalecchio di Reno (BO) Italy
www.cineca.it Tel: +39 051 6171722
g.fatigati [AT] cineca.it
