In a message dated 7/7/2005 10:39:48 A.M. Central Daylight Time, [EMAIL PROTECTED] writes:
It's probably worth saying that support was up to 24 processors (the sum of CPs and zAAPs) in a single z/OS image at GA, and is now up to 32 processors in a single image. Obviously I missed some processor announcements. I know what an Instruction Processor and an I/O Processor are, but what is a zAAP? In what IBM book might I learn more about configurations that have >16 processors? I cannot find "AAP" in the z/Arch PoO book. And I am very curious as to how IBM managed to make z/OS work with more than 16 Instruction Processors in one image. E.g., how is the 17th CPU supported with the 16-bit CPU affinity mask in the SRB and all the other various 16-bit CPU masks imbedded at least in the Control Program? Bill Fairchild ---------------------------------------------------------------------- For IBM-MAIN subscribe / signoff / archive access instructions, send email to [EMAIL PROTECTED] with the message: GET IBM-MAIN INFO Search the archives at http://bama.ua.edu/archives/ibm-main.html
