In a recent note, Craddock, Chris said: > Date: Thu, 14 Jul 2005 09:21:08 -0500 > > > Another surprise (?) was that two STs were faster than an STM > > for two registers. > > Once again, no big surprise in terms of cache and memory > design. It might even turn out that the advantage holds true > for a larger number of registers. Try it. > Might this also depend on whether the storage operand is doubleword aligned, and whether the registers are an even/odd pair?
I once heard a rumor that there was special millicode to optimize "STM R14,R12". A programmer I know once discovered that (on a 148?) LM; STM moved a doubleword faster than MVC. He accordingly updated all his assembly code. He was livid when we got a Magnusson M80, marketed to compete with the 148, and discovered that MVC was faster than LM; STM. A true Blue partisan, he had to confront the choice of optimizing his code for competing hardware or leaving it suboptimal. He was not in the least soothed that the M80 executed neither instruction slower than the 148. > And in any case "who cares"? > See above. -- gil -- StorageTek INFORMATION made POWERFUL ---------------------------------------------------------------------- For IBM-MAIN subscribe / signoff / archive access instructions, send email to [EMAIL PROTECTED] with the message: GET IBM-MAIN INFO Search the archives at http://bama.ua.edu/archives/ibm-main.html
