On Fri, 29 Jul 2005 15:25:49 -0700, Edward E. Jaffe
<[EMAIL PROTECTED]> wrote:

>Tom Schmidt wrote:
>
>>My reaction is similar to yours, Ed.  I had been wondering about the need
>>for some kind of "come from" display when IBM brought branch relative
long
>>instructions to the architecture.  The R15/R14 game seems like it falls
>>apart if the arrival at location 0 (or just arbitrary low storage) came
>>about because of a branch relative (jump) or worse, a BR-long.
>>
>>
>
>I'm glad you agree with me, Tom. But, I honestly don't see how the
>advent of relative branch has compounded this long-standing issue in any
>way. I consider the possibility of a relative branch becoming "wild" to
>be quite remote. (One of their chief benefits!) Remember, they don't
>depend on a GPR being loaded correctly and/or an associated USING being
>properly specified. They are always relative to the current PSW.
>
>For example, ,'BC 15,0(0,0)' will definitely go to location zero and
>leave no linkage trail in a register. How would you even code (on
>purpose or by accident) a BRC or BRCL to branch to location zero?
>Likewise, 'BAS xx,0(0,0)' will definitely go to location zero, but there
>will be a linkage register trail. Again, I don't see how you would even
>code the equivalent relative instructions BRAS or BRASL to branch there.

Never say never:  Consider a badly constructed base for an EXecute
instruction that "happens" to address an X'C0' "somewhere in virtual
storage".  The X'C0' is interpretted by the processor as a valid BRC
instruction and... off we go!

Granted this should be a rare event, but then the non-rare events are
supposed to be handled by the applications folks themselves thus leaving
these WTF-events to us to marvel over.

I have not come up with any cases where your favorite future instruction -
EXR - could cause such weirdness, by the way.

(There may be more wonderous cases to be found - I don't know (yet).)

--
Tom Schmidt
Madison, WI

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